In the recent development of CMOS technology for designing low power consumption and high functionality chips, the problem of soft error generation has frequently been encountered. Soft error generation is the random generation of alpha particles from lead-containing interconnects which produces an electrical noise that is comparable to the low power signal in the chips. As a result, the integrated circuit chip has a significant soft error rate (SER). One obvious solution for the soft error generation problem is the use of lead-containing solder that has acceptably low alpha emission. However, this type of lead-containing solder is significantly more expensive and therefore presenting a limiting factor for the further development of present C4 (controlled collapse chip connection) technology. The C4 technology is a lead-rich lead/tin alloy used to interconnect chips directly to circuit boards which is widely used in the semiconductor industry.
The alpha-induced SER is driven by the presence of radioactive impurities in the C4 lead. In contrast to cosmic SER, alpha-induced SER is highly sensitive to Q.sub.crit (the amount of charge injected into a mode that will modify the state of a circuit). At approximately 20 fC of Q.sub.crit, alpha SER begins to dominate over cosmic SER and increases with decreasing Q.sub.crit at a rate of 10.times.per 2.about.3 fC. The rate is reduced at Q.sub.crit s of less than 16 f. The smallest CMOS 6's SRAM cells have nominal Q.sub.crit s as low as 17 fC, resulting in SER's of 8 PPM/K-bit/Khr (or 1 fail/M-bit/12 yrs). Some CMOS 6's dynamic logic circuits in high-end products have been identified as having nominal Q.sub.crit s of 20 fC. Therefore, C4 alpha-induced SER can no longer be ignored in the design of a CMOS logic circuitry. The alpha SER concern is accentuated due to the direct scaling or migration of these circuits into CMOS 7's which decreases Q.sub.crit by as much as 2.times.(10 fC Q.sub.crit s will yield SER of approximately 100 ppm/k-ckt/khr=1 fail/M-ckt/yr). It is therefore necessary to consider the effect of SER along with the density/performance/power/reliability trade-offs that are usually encountered in modern chip design.
It is therefore an object of the present invention to provide an interconnect system that has low alpha particle emission characteristics that does not have the drawbacks or shortcomings of conventional lead-based interconnect systems.
It is another object of the present invention to provide in interconnect system that has low alpha particle emission characteristics for use in an electronic device that utilizes lead-free conductive bumps positioned on the surface of a semiconductor chip.
It is a further object of the present invention to provide an interconnect system that has low alpha particle emission characteristic for use in a semiconductor chip by utilizing conductive bumps that are formed of polymeric binder and metal particles.
It is still another object of the present invention to provide an interconnect system that has low alpha particle emission characteristics such that the soft error generation can be minimized.
It is another further object of the present invention to provide an interconnect system that has low alpha particle emission characteristics for use in a semiconductor device wherein conductive bumps formed of thermoplastic polymeric binder and metal flakes of a nobel metal are utilized.
It is yet another object of the present invention to provide an interconnect system that has low alpha particle emission characteristics for use in a semiconductor device including an IC chip that has conductive bumps built on the surface by composite material formed from a polymer and metal particles and a substrate that has conductive regions thereon bonded to the conductive bumps.
It is still another further object of the present invention to provide a method of making an interconnect system that has low alpha particle emission characteristics for use in an electronic device by bonding the conductive bumps formed of a polymer and metal particles to the conductive regions on a substrate.